1463 lines
32 KiB
C
1463 lines
32 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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*/
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#include <dt-bindings/interconnect/qcom,cinder.h>
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#include <linux/device.h>
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#include <linux/interconnect.h>
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#include <linux/interconnect-provider.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include "icc-rpmh.h"
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#include "qnoc-qos.h"
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static const struct regmap_config icc_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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};
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static struct qcom_icc_node qup0_core_master = {
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.name = "qup0_core_master",
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.id = MASTER_QUP_CORE_0,
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.channels = 1,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 1,
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.links = { SLAVE_QUP_CORE_0 },
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};
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static struct qcom_icc_node qup1_core_master = {
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.name = "qup1_core_master",
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.id = MASTER_QUP_CORE_1,
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.channels = 1,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 1,
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.links = { SLAVE_QUP_CORE_1 },
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};
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static struct qcom_icc_qosbox alm_sys_tcu_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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.offsets = { 0xb1000 },
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.config = &(struct qos_config) {
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.prio = 6,
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.urg_fwd = 0,
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.prio_fwd_disable = 1,
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},
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};
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static struct qcom_icc_node alm_sys_tcu = {
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.name = "alm_sys_tcu",
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.id = MASTER_SYS_TCU,
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.channels = 1,
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.buswidth = 8,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &alm_sys_tcu_qos,
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.num_links = 2,
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.links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC },
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};
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static struct qcom_icc_node chm_apps = {
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.name = "chm_apps",
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.id = MASTER_APPSS_PROC,
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.channels = 1,
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.buswidth = 16,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 4,
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.links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC,
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SLAVE_GEMNOC_MODEM_CNOC, SLAVE_MEM_NOC_PCIE_SNOC
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},
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};
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static struct qcom_icc_qosbox qnm_ecpri_dma_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 2,
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.offsets = { 0xb7000, 0xb8000 },
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.config = &(struct qos_config) {
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.prio = 0,
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.urg_fwd = 1,
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.prio_fwd_disable = 0,
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},
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};
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static struct qcom_icc_node qnm_ecpri_dma = {
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.name = "qnm_ecpri_dma",
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.id = MASTER_GEMNOC_ECPRI_DMA,
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.channels = 2,
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.buswidth = 32,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &qnm_ecpri_dma_qos,
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.num_links = 2,
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.links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC },
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};
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static struct qcom_icc_qosbox qnm_fec_2_gemnoc_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 2,
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.offsets = { 0xaf000, 0xb0000 },
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.config = &(struct qos_config) {
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.prio = 0,
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.urg_fwd = 1,
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.prio_fwd_disable = 0,
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},
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};
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static struct qcom_icc_node qnm_fec_2_gemnoc = {
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.name = "qnm_fec_2_gemnoc",
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.id = MASTER_FEC_2_GEMNOC,
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.channels = 2,
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.buswidth = 32,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &qnm_fec_2_gemnoc_qos,
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.num_links = 2,
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.links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC },
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};
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static struct qcom_icc_qosbox qnm_pcie_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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.offsets = { 0xb3000 },
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.config = &(struct qos_config) {
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.prio = 0,
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.urg_fwd = 1,
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.prio_fwd_disable = 0,
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},
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};
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static struct qcom_icc_node qnm_pcie = {
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.name = "qnm_pcie",
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.id = MASTER_ANOC_PCIE_GEM_NOC,
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.channels = 1,
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.buswidth = 64,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &qnm_pcie_qos,
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.num_links = 3,
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.links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC,
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SLAVE_GEMNOC_MODEM_CNOC
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},
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};
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static struct qcom_icc_qosbox qnm_snoc_gc_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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.offsets = { 0xb5000 },
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.config = &(struct qos_config) {
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.prio = 0,
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.urg_fwd = 1,
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.prio_fwd_disable = 0,
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},
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};
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static struct qcom_icc_node qnm_snoc_gc = {
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.name = "qnm_snoc_gc",
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.id = MASTER_SNOC_GC_MEM_NOC,
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.channels = 1,
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.buswidth = 8,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &qnm_snoc_gc_qos,
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.num_links = 1,
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.links = { SLAVE_LLCC },
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};
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static struct qcom_icc_qosbox qnm_snoc_sf_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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.offsets = { 0xb6000 },
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.config = &(struct qos_config) {
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.prio = 0,
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.urg_fwd = 1,
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.prio_fwd_disable = 0,
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},
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};
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static struct qcom_icc_node qnm_snoc_sf = {
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.name = "qnm_snoc_sf",
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.id = MASTER_SNOC_SF_MEM_NOC,
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.channels = 1,
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.buswidth = 16,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &qnm_snoc_sf_qos,
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.num_links = 4,
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.links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC,
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SLAVE_GEMNOC_MODEM_CNOC, SLAVE_MEM_NOC_PCIE_SNOC
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},
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};
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static struct qcom_icc_node qxm_mdsp = {
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.name = "qxm_mdsp",
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.id = MASTER_MSS_PROC,
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.channels = 1,
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.buswidth = 16,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 3,
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.links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC,
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SLAVE_MEM_NOC_PCIE_SNOC
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},
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};
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static struct qcom_icc_node llcc_mc = {
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.name = "llcc_mc",
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.id = MASTER_LLCC,
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.channels = 8,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 1,
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.links = { SLAVE_EBI1 },
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};
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static struct qcom_icc_qosbox qhm_gic_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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.offsets = { 0x45000 },
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.config = &(struct qos_config) {
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.prio = 0,
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.urg_fwd = 0,
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.prio_fwd_disable = 1,
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},
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};
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static struct qcom_icc_node qhm_gic = {
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.name = "qhm_gic",
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.id = MASTER_GIC_AHB,
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.channels = 1,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &qhm_gic_qos,
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.num_links = 1,
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.links = { SLAVE_SNOC_GEM_NOC_SF },
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};
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static struct qcom_icc_qosbox qhm_qdss_bam_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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.offsets = { 0x44000 },
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.config = &(struct qos_config) {
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.prio = 0,
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.urg_fwd = 0,
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.prio_fwd_disable = 1,
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},
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};
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static struct qcom_icc_node qhm_qdss_bam = {
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.name = "qhm_qdss_bam",
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.id = MASTER_QDSS_BAM,
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.channels = 1,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &qhm_qdss_bam_qos,
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.num_links = 1,
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.links = { SLAVE_SNOC_GEM_NOC_SF },
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};
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static struct qcom_icc_qosbox qhm_qpic_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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.offsets = { 0x43000 },
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.config = &(struct qos_config) {
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.prio = 0,
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.urg_fwd = 0,
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.prio_fwd_disable = 1,
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},
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};
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static struct qcom_icc_node qhm_qpic = {
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.name = "qhm_qpic",
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.id = MASTER_QPIC,
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.channels = 1,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &qhm_qpic_qos,
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.num_links = 1,
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.links = { SLAVE_A1NOC_SNOC },
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};
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static struct qcom_icc_qosbox qhm_qspi_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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.offsets = { 0x42000 },
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.config = &(struct qos_config) {
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.prio = 0,
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.urg_fwd = 0,
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.prio_fwd_disable = 1,
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},
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};
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static struct qcom_icc_node qhm_qspi = {
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.name = "qhm_qspi",
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.id = MASTER_QSPI_0,
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.channels = 1,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &qhm_qspi_qos,
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.num_links = 1,
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.links = { SLAVE_A1NOC_SNOC },
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};
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static struct qcom_icc_qosbox qhm_qup0_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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.offsets = { 0x41000 },
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.config = &(struct qos_config) {
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.prio = 0,
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.urg_fwd = 0,
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.prio_fwd_disable = 1,
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},
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};
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static struct qcom_icc_node qhm_qup0 = {
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.name = "qhm_qup0",
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.id = MASTER_QUP_0,
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.channels = 1,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &qhm_qup0_qos,
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.num_links = 1,
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.links = { SLAVE_A1NOC_SNOC },
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};
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static struct qcom_icc_qosbox qhm_qup1_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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.offsets = { 0x40000 },
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.config = &(struct qos_config) {
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.prio = 0,
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.urg_fwd = 0,
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.prio_fwd_disable = 1,
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},
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};
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static struct qcom_icc_node qhm_qup1 = {
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.name = "qhm_qup1",
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.id = MASTER_QUP_1,
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.channels = 1,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &qhm_qup1_qos,
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.num_links = 1,
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.links = { SLAVE_A1NOC_SNOC },
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};
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static struct qcom_icc_node qhm_system_noc_cfg = {
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.name = "qhm_system_noc_cfg",
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.id = MASTER_SNOC_CFG,
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.channels = 1,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 1,
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.links = { SLAVE_SERVICE_SNOC },
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};
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static struct qcom_icc_node qnm_aggre_noc = {
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.name = "qnm_aggre_noc",
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.id = MASTER_ANOC_SNOC,
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.channels = 1,
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.buswidth = 8,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 1,
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.links = { SLAVE_SNOC_GEM_NOC_SF },
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};
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static struct qcom_icc_node qnm_aggre_noc_gsi = {
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.name = "qnm_aggre_noc_gsi",
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.id = MASTER_ANOC_GSI,
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.channels = 1,
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.buswidth = 8,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 1,
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.links = { SLAVE_SNOC_GEM_NOC_GC },
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};
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static struct qcom_icc_node qnm_gemnoc_cnoc = {
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.name = "qnm_gemnoc_cnoc",
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.id = MASTER_GEM_NOC_CNOC,
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.channels = 1,
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.buswidth = 16,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 36,
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.links = { SLAVE_AHB2PHY_SOUTH, SLAVE_AHB2PHY_NORTH,
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SLAVE_AHB2PHY_EAST, SLAVE_AOSS,
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SLAVE_CLK_CTL, SLAVE_RBCPR_CX_CFG,
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SLAVE_RBCPR_MX_CFG, SLAVE_CRYPTO_0_CFG,
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SLAVE_ECPRI_CFG, SLAVE_IMEM_CFG,
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SLAVE_IPC_ROUTER_CFG, SLAVE_CNOC_MSS,
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SLAVE_PCIE_CFG, SLAVE_PDM,
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SLAVE_PIMEM_CFG, SLAVE_PRNG,
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SLAVE_QDSS_CFG, SLAVE_QPIC,
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SLAVE_QSPI_0, SLAVE_QUP_0,
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SLAVE_QUP_1, SLAVE_SDCC_2,
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SLAVE_SMBUS_CFG, SLAVE_SNOC_CFG,
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SLAVE_TCSR, SLAVE_TLMM,
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SLAVE_TME_CFG, SLAVE_TSC_CFG,
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SLAVE_USB3_0, SLAVE_VSENSE_CTRL_CFG,
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SLAVE_DDRSS_CFG, SLAVE_IMEM,
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SLAVE_PIMEM, SLAVE_ETHERNET_SS,
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SLAVE_QDSS_STM, SLAVE_TCU
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},
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};
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static struct qcom_icc_node qnm_gemnoc_modem_slave = {
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.name = "qnm_gemnoc_modem_slave",
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.id = MASTER_GEMNOC_MODEM_CNOC,
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.channels = 1,
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.buswidth = 16,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 1,
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.links = { SLAVE_MODEM_OFFLINE },
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};
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static struct qcom_icc_node qnm_gemnoc_pcie = {
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.name = "qnm_gemnoc_pcie",
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.id = MASTER_GEM_NOC_PCIE_SNOC,
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.channels = 1,
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.buswidth = 16,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 1,
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.links = { SLAVE_PCIE_0 },
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};
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static struct qcom_icc_qosbox qxm_crypto_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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.offsets = { 0x3f000 },
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.config = &(struct qos_config) {
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.prio = 0,
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.urg_fwd = 0,
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.prio_fwd_disable = 1,
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},
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};
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static struct qcom_icc_node qxm_crypto = {
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.name = "qxm_crypto",
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.id = MASTER_CRYPTO,
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.channels = 1,
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.buswidth = 8,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &qxm_crypto_qos,
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.num_links = 1,
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.links = { SLAVE_A1NOC_SNOC },
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};
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static struct qcom_icc_qosbox qxm_ecpri_gsi_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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.offsets = { 0x3e000 },
|
|
.config = &(struct qos_config) {
|
|
.prio = 2,
|
|
.urg_fwd = 0,
|
|
.prio_fwd_disable = 1,
|
|
},
|
|
};
|
|
|
|
static struct qcom_icc_node qxm_ecpri_gsi = {
|
|
.name = "qxm_ecpri_gsi",
|
|
.id = MASTER_ECPRI_GSI,
|
|
.channels = 1,
|
|
.buswidth = 8,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.qosbox = &qxm_ecpri_gsi_qos,
|
|
.num_links = 2,
|
|
.links = { SLAVE_ANOC_SNOC_GSI, SLAVE_PCIE_0 },
|
|
};
|
|
|
|
static struct qcom_icc_qosbox qxm_pimem_qos = {
|
|
.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
|
|
.num_ports = 1,
|
|
.offsets = { 0x3d000 },
|
|
.config = &(struct qos_config) {
|
|
.prio = 0,
|
|
.urg_fwd = 0,
|
|
.prio_fwd_disable = 1,
|
|
},
|
|
};
|
|
|
|
static struct qcom_icc_node qxm_pimem = {
|
|
.name = "qxm_pimem",
|
|
.id = MASTER_PIMEM,
|
|
.channels = 1,
|
|
.buswidth = 8,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.qosbox = &qxm_pimem_qos,
|
|
.num_links = 1,
|
|
.links = { SLAVE_SNOC_GEM_NOC_GC },
|
|
};
|
|
|
|
static struct qcom_icc_qosbox xm_ecpri_dma_qos = {
|
|
.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
|
|
.num_ports = 2,
|
|
.offsets = { 0x3b000, 0x3c000 },
|
|
.config = &(struct qos_config) {
|
|
.prio = 2,
|
|
.urg_fwd = 0,
|
|
.prio_fwd_disable = 1,
|
|
},
|
|
};
|
|
|
|
static struct qcom_icc_node xm_ecpri_dma = {
|
|
.name = "xm_ecpri_dma",
|
|
.id = MASTER_SNOC_ECPRI_DMA,
|
|
.channels = 2,
|
|
.buswidth = 32,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.qosbox = &xm_ecpri_dma_qos,
|
|
.num_links = 2,
|
|
.links = { SLAVE_ECPRI_GEMNOC, SLAVE_PCIE_0 },
|
|
};
|
|
|
|
static struct qcom_icc_qosbox xm_gic_qos = {
|
|
.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
|
|
.num_ports = 1,
|
|
.offsets = { 0x3a000 },
|
|
.config = &(struct qos_config) {
|
|
.prio = 0,
|
|
.urg_fwd = 0,
|
|
.prio_fwd_disable = 1,
|
|
},
|
|
};
|
|
|
|
static struct qcom_icc_node xm_gic = {
|
|
.name = "xm_gic",
|
|
.id = MASTER_GIC,
|
|
.channels = 1,
|
|
.buswidth = 8,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.qosbox = &xm_gic_qos,
|
|
.num_links = 1,
|
|
.links = { SLAVE_SNOC_GEM_NOC_GC },
|
|
};
|
|
|
|
static struct qcom_icc_qosbox xm_pcie_qos = {
|
|
.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
|
|
.num_ports = 1,
|
|
.offsets = { 0x39000 },
|
|
.config = &(struct qos_config) {
|
|
.prio = 2,
|
|
.urg_fwd = 0,
|
|
.prio_fwd_disable = 1,
|
|
},
|
|
};
|
|
|
|
static struct qcom_icc_node xm_pcie = {
|
|
.name = "xm_pcie",
|
|
.id = MASTER_PCIE,
|
|
.channels = 1,
|
|
.buswidth = 64,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.qosbox = &xm_pcie_qos,
|
|
.num_links = 1,
|
|
.links = { SLAVE_ANOC_PCIE_GEM_NOC },
|
|
};
|
|
|
|
static struct qcom_icc_qosbox xm_qdss_etr0_qos = {
|
|
.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
|
|
.num_ports = 1,
|
|
.offsets = { 0x38000 },
|
|
.config = &(struct qos_config) {
|
|
.prio = 0,
|
|
.urg_fwd = 0,
|
|
.prio_fwd_disable = 1,
|
|
},
|
|
};
|
|
|
|
static struct qcom_icc_node xm_qdss_etr0 = {
|
|
.name = "xm_qdss_etr0",
|
|
.id = MASTER_QDSS_ETR,
|
|
.channels = 1,
|
|
.buswidth = 8,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.qosbox = &xm_qdss_etr0_qos,
|
|
.num_links = 1,
|
|
.links = { SLAVE_SNOC_GEM_NOC_SF },
|
|
};
|
|
|
|
static struct qcom_icc_qosbox xm_qdss_etr1_qos = {
|
|
.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
|
|
.num_ports = 1,
|
|
.offsets = { 0x37000 },
|
|
.config = &(struct qos_config) {
|
|
.prio = 0,
|
|
.urg_fwd = 0,
|
|
.prio_fwd_disable = 1,
|
|
},
|
|
};
|
|
|
|
static struct qcom_icc_node xm_qdss_etr1 = {
|
|
.name = "xm_qdss_etr1",
|
|
.id = MASTER_QDSS_ETR_1,
|
|
.channels = 1,
|
|
.buswidth = 8,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.qosbox = &xm_qdss_etr1_qos,
|
|
.num_links = 1,
|
|
.links = { SLAVE_SNOC_GEM_NOC_SF },
|
|
};
|
|
|
|
static struct qcom_icc_qosbox xm_sdc_qos = {
|
|
.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
|
|
.num_ports = 1,
|
|
.offsets = { 0x36000 },
|
|
.config = &(struct qos_config) {
|
|
.prio = 0,
|
|
.urg_fwd = 0,
|
|
.prio_fwd_disable = 1,
|
|
},
|
|
};
|
|
|
|
static struct qcom_icc_node xm_sdc = {
|
|
.name = "xm_sdc",
|
|
.id = MASTER_SDCC_1,
|
|
.channels = 1,
|
|
.buswidth = 8,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.qosbox = &xm_sdc_qos,
|
|
.num_links = 1,
|
|
.links = { SLAVE_A1NOC_SNOC },
|
|
};
|
|
|
|
static struct qcom_icc_qosbox xm_usb3_qos = {
|
|
.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
|
|
.num_ports = 1,
|
|
.offsets = { 0x35000 },
|
|
.config = &(struct qos_config) {
|
|
.prio = 0,
|
|
.urg_fwd = 0,
|
|
.prio_fwd_disable = 1,
|
|
},
|
|
};
|
|
|
|
static struct qcom_icc_node xm_usb3 = {
|
|
.name = "xm_usb3",
|
|
.id = MASTER_USB3,
|
|
.channels = 1,
|
|
.buswidth = 8,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.qosbox = &xm_usb3_qos,
|
|
.num_links = 1,
|
|
.links = { SLAVE_A1NOC_SNOC },
|
|
};
|
|
|
|
static struct qcom_icc_node qup0_core_slave = {
|
|
.name = "qup0_core_slave",
|
|
.id = SLAVE_QUP_CORE_0,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qup1_core_slave = {
|
|
.name = "qup1_core_slave",
|
|
.id = SLAVE_QUP_CORE_1,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qns_gem_noc_cnoc = {
|
|
.name = "qns_gem_noc_cnoc",
|
|
.id = SLAVE_GEM_NOC_CNOC,
|
|
.channels = 1,
|
|
.buswidth = 16,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 1,
|
|
.links = { MASTER_GEM_NOC_CNOC },
|
|
};
|
|
|
|
static struct qcom_icc_node qns_llcc = {
|
|
.name = "qns_llcc",
|
|
.id = SLAVE_LLCC,
|
|
.channels = 8,
|
|
.buswidth = 16,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 1,
|
|
.links = { MASTER_LLCC },
|
|
};
|
|
|
|
static struct qcom_icc_node qns_modem_slave = {
|
|
.name = "qns_modem_slave",
|
|
.id = SLAVE_GEMNOC_MODEM_CNOC,
|
|
.channels = 1,
|
|
.buswidth = 16,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 1,
|
|
.links = { MASTER_GEMNOC_MODEM_CNOC },
|
|
};
|
|
|
|
static struct qcom_icc_node qns_pcie = {
|
|
.name = "qns_pcie",
|
|
.id = SLAVE_MEM_NOC_PCIE_SNOC,
|
|
.channels = 1,
|
|
.buswidth = 16,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 1,
|
|
.links = { MASTER_GEM_NOC_PCIE_SNOC },
|
|
};
|
|
|
|
static struct qcom_icc_node ebi = {
|
|
.name = "ebi",
|
|
.id = SLAVE_EBI1,
|
|
.channels = 8,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_ahb2phy0_south = {
|
|
.name = "qhs_ahb2phy0_south",
|
|
.id = SLAVE_AHB2PHY_SOUTH,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_ahb2phy1_north = {
|
|
.name = "qhs_ahb2phy1_north",
|
|
.id = SLAVE_AHB2PHY_NORTH,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_ahb2phy2_east = {
|
|
.name = "qhs_ahb2phy2_east",
|
|
.id = SLAVE_AHB2PHY_EAST,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_aoss = {
|
|
.name = "qhs_aoss",
|
|
.id = SLAVE_AOSS,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_clk_ctl = {
|
|
.name = "qhs_clk_ctl",
|
|
.id = SLAVE_CLK_CTL,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_cpr_cx = {
|
|
.name = "qhs_cpr_cx",
|
|
.id = SLAVE_RBCPR_CX_CFG,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_cpr_mx = {
|
|
.name = "qhs_cpr_mx",
|
|
.id = SLAVE_RBCPR_MX_CFG,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_crypto_cfg = {
|
|
.name = "qhs_crypto_cfg",
|
|
.id = SLAVE_CRYPTO_0_CFG,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_ecpri_cfg = {
|
|
.name = "qhs_ecpri_cfg",
|
|
.id = SLAVE_ECPRI_CFG,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_imem_cfg = {
|
|
.name = "qhs_imem_cfg",
|
|
.id = SLAVE_IMEM_CFG,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_ipc_router = {
|
|
.name = "qhs_ipc_router",
|
|
.id = SLAVE_IPC_ROUTER_CFG,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_mss_cfg = {
|
|
.name = "qhs_mss_cfg",
|
|
.id = SLAVE_CNOC_MSS,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_pcie_cfg = {
|
|
.name = "qhs_pcie_cfg",
|
|
.id = SLAVE_PCIE_CFG,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_pdm = {
|
|
.name = "qhs_pdm",
|
|
.id = SLAVE_PDM,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_pimem_cfg = {
|
|
.name = "qhs_pimem_cfg",
|
|
.id = SLAVE_PIMEM_CFG,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_prng = {
|
|
.name = "qhs_prng",
|
|
.id = SLAVE_PRNG,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_qdss_cfg = {
|
|
.name = "qhs_qdss_cfg",
|
|
.id = SLAVE_QDSS_CFG,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_qpic = {
|
|
.name = "qhs_qpic",
|
|
.id = SLAVE_QPIC,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_qspi = {
|
|
.name = "qhs_qspi",
|
|
.id = SLAVE_QSPI_0,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_qup0 = {
|
|
.name = "qhs_qup0",
|
|
.id = SLAVE_QUP_0,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_qup1 = {
|
|
.name = "qhs_qup1",
|
|
.id = SLAVE_QUP_1,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_sdc2 = {
|
|
.name = "qhs_sdc2",
|
|
.id = SLAVE_SDCC_2,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_smbus_cfg = {
|
|
.name = "qhs_smbus_cfg",
|
|
.id = SLAVE_SMBUS_CFG,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_system_noc_cfg = {
|
|
.name = "qhs_system_noc_cfg",
|
|
.id = SLAVE_SNOC_CFG,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 1,
|
|
.links = { MASTER_SNOC_CFG },
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_tcsr = {
|
|
.name = "qhs_tcsr",
|
|
.id = SLAVE_TCSR,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_tlmm = {
|
|
.name = "qhs_tlmm",
|
|
.id = SLAVE_TLMM,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_tme_cfg = {
|
|
.name = "qhs_tme_cfg",
|
|
.id = SLAVE_TME_CFG,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_tsc_cfg = {
|
|
.name = "qhs_tsc_cfg",
|
|
.id = SLAVE_TSC_CFG,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_usb3 = {
|
|
.name = "qhs_usb3",
|
|
.id = SLAVE_USB3_0,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
|
|
.name = "qhs_vsense_ctrl_cfg",
|
|
.id = SLAVE_VSENSE_CTRL_CFG,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qns_a1noc_snoc = {
|
|
.name = "qns_a1noc_snoc",
|
|
.id = SLAVE_A1NOC_SNOC,
|
|
.channels = 1,
|
|
.buswidth = 8,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 1,
|
|
.links = { MASTER_ANOC_SNOC },
|
|
};
|
|
|
|
static struct qcom_icc_node qns_anoc_snoc_gsi = {
|
|
.name = "qns_anoc_snoc_gsi",
|
|
.id = SLAVE_ANOC_SNOC_GSI,
|
|
.channels = 1,
|
|
.buswidth = 8,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 1,
|
|
.links = { MASTER_ANOC_GSI },
|
|
};
|
|
|
|
static struct qcom_icc_node qns_ddrss_cfg = {
|
|
.name = "qns_ddrss_cfg",
|
|
.id = SLAVE_DDRSS_CFG,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qns_ecpri_gemnoc = {
|
|
.name = "qns_ecpri_gemnoc",
|
|
.id = SLAVE_ECPRI_GEMNOC,
|
|
.channels = 2,
|
|
.buswidth = 32,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 1,
|
|
.links = { MASTER_GEMNOC_ECPRI_DMA },
|
|
};
|
|
|
|
static struct qcom_icc_node qns_gemnoc_gc = {
|
|
.name = "qns_gemnoc_gc",
|
|
.id = SLAVE_SNOC_GEM_NOC_GC,
|
|
.channels = 1,
|
|
.buswidth = 8,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 1,
|
|
.links = { MASTER_SNOC_GC_MEM_NOC },
|
|
};
|
|
|
|
static struct qcom_icc_node qns_gemnoc_sf = {
|
|
.name = "qns_gemnoc_sf",
|
|
.id = SLAVE_SNOC_GEM_NOC_SF,
|
|
.channels = 1,
|
|
.buswidth = 16,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 1,
|
|
.links = { MASTER_SNOC_SF_MEM_NOC },
|
|
};
|
|
|
|
static struct qcom_icc_node qns_modem = {
|
|
.name = "qns_modem",
|
|
.id = SLAVE_MODEM_OFFLINE,
|
|
.channels = 1,
|
|
.buswidth = 32,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qns_pcie_gemnoc = {
|
|
.name = "qns_pcie_gemnoc",
|
|
.id = SLAVE_ANOC_PCIE_GEM_NOC,
|
|
.channels = 1,
|
|
.buswidth = 64,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 1,
|
|
.links = { MASTER_ANOC_PCIE_GEM_NOC },
|
|
};
|
|
|
|
static struct qcom_icc_node qxs_imem = {
|
|
.name = "qxs_imem",
|
|
.id = SLAVE_IMEM,
|
|
.channels = 1,
|
|
.buswidth = 8,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node qxs_pimem = {
|
|
.name = "qxs_pimem",
|
|
.id = SLAVE_PIMEM,
|
|
.channels = 1,
|
|
.buswidth = 8,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node srvc_system_noc = {
|
|
.name = "srvc_system_noc",
|
|
.id = SLAVE_SERVICE_SNOC,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node xs_ethernet_ss = {
|
|
.name = "xs_ethernet_ss",
|
|
.id = SLAVE_ETHERNET_SS,
|
|
.channels = 1,
|
|
.buswidth = 32,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node xs_pcie = {
|
|
.name = "xs_pcie",
|
|
.id = SLAVE_PCIE_0,
|
|
.channels = 1,
|
|
.buswidth = 64,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node xs_qdss_stm = {
|
|
.name = "xs_qdss_stm",
|
|
.id = SLAVE_QDSS_STM,
|
|
.channels = 1,
|
|
.buswidth = 4,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_node xs_sys_tcu_cfg = {
|
|
.name = "xs_sys_tcu_cfg",
|
|
.id = SLAVE_TCU,
|
|
.channels = 1,
|
|
.buswidth = 8,
|
|
.noc_ops = &qcom_qnoc4_ops,
|
|
.num_links = 0,
|
|
};
|
|
|
|
static struct qcom_icc_bcm bcm_acv = {
|
|
.name = "ACV",
|
|
.voter_idx = 0,
|
|
.enable_mask = 0x8,
|
|
.num_nodes = 1,
|
|
.nodes = { &ebi },
|
|
};
|
|
|
|
static struct qcom_icc_bcm bcm_ce0 = {
|
|
.name = "CE0",
|
|
.voter_idx = 0,
|
|
.num_nodes = 1,
|
|
.nodes = { &qxm_crypto },
|
|
};
|
|
|
|
static struct qcom_icc_bcm bcm_cn0 = {
|
|
.name = "CN0",
|
|
.voter_idx = 0,
|
|
.enable_mask = 0x1,
|
|
.num_nodes = 44,
|
|
.nodes = { &qhm_qpic, &qhm_qspi,
|
|
&qnm_gemnoc_cnoc, &qnm_gemnoc_modem_slave,
|
|
&qnm_gemnoc_pcie, &xm_sdc,
|
|
&xm_usb3, &qhs_ahb2phy0_south,
|
|
&qhs_ahb2phy1_north, &qhs_ahb2phy2_east,
|
|
&qhs_aoss, &qhs_clk_ctl,
|
|
&qhs_cpr_cx, &qhs_cpr_mx,
|
|
&qhs_crypto_cfg, &qhs_ecpri_cfg,
|
|
&qhs_imem_cfg, &qhs_ipc_router,
|
|
&qhs_mss_cfg, &qhs_pcie_cfg,
|
|
&qhs_pdm, &qhs_pimem_cfg,
|
|
&qhs_prng, &qhs_qdss_cfg,
|
|
&qhs_qpic, &qhs_qspi,
|
|
&qhs_qup0, &qhs_qup1,
|
|
&qhs_sdc2, &qhs_smbus_cfg,
|
|
&qhs_system_noc_cfg, &qhs_tcsr,
|
|
&qhs_tlmm, &qhs_tme_cfg,
|
|
&qhs_tsc_cfg, &qhs_usb3,
|
|
&qhs_vsense_ctrl_cfg, &qns_ddrss_cfg,
|
|
&qns_modem, &qxs_imem,
|
|
&qxs_pimem, &xs_ethernet_ss,
|
|
&xs_qdss_stm, &xs_sys_tcu_cfg
|
|
},
|
|
};
|
|
|
|
static struct qcom_icc_bcm bcm_mc0 = {
|
|
.name = "MC0",
|
|
.voter_idx = 0,
|
|
.num_nodes = 1,
|
|
.nodes = { &ebi },
|
|
};
|
|
|
|
static struct qcom_icc_bcm bcm_qup0 = {
|
|
.name = "QUP0",
|
|
.voter_idx = 0,
|
|
.num_nodes = 2,
|
|
.nodes = { &qup0_core_slave, &qup1_core_slave },
|
|
};
|
|
|
|
static struct qcom_icc_bcm bcm_sh0 = {
|
|
.name = "SH0",
|
|
.voter_idx = 0,
|
|
.num_nodes = 1,
|
|
.nodes = { &qns_llcc },
|
|
};
|
|
|
|
static struct qcom_icc_bcm bcm_sh1 = {
|
|
.name = "SH1",
|
|
.voter_idx = 0,
|
|
.enable_mask = 0x1,
|
|
.num_nodes = 11,
|
|
.nodes = { &alm_sys_tcu, &chm_apps,
|
|
&qnm_ecpri_dma, &qnm_fec_2_gemnoc,
|
|
&qnm_pcie, &qnm_snoc_gc,
|
|
&qnm_snoc_sf, &qxm_mdsp,
|
|
&qns_gem_noc_cnoc, &qns_modem_slave,
|
|
&qns_pcie
|
|
},
|
|
};
|
|
|
|
static struct qcom_icc_bcm bcm_sn0 = {
|
|
.name = "SN0",
|
|
.voter_idx = 0,
|
|
.num_nodes = 1,
|
|
.nodes = { &qns_gemnoc_sf },
|
|
};
|
|
|
|
static struct qcom_icc_bcm bcm_sn1 = {
|
|
.name = "SN1",
|
|
.voter_idx = 0,
|
|
.enable_mask = 0x1,
|
|
.num_nodes = 6,
|
|
.nodes = { &qhm_gic, &qxm_pimem,
|
|
&xm_gic, &xm_qdss_etr0,
|
|
&xm_qdss_etr1, &qns_gemnoc_gc
|
|
},
|
|
};
|
|
|
|
static struct qcom_icc_bcm bcm_sn2 = {
|
|
.name = "SN2",
|
|
.voter_idx = 0,
|
|
.num_nodes = 5,
|
|
.nodes = { &qnm_aggre_noc, &qxm_ecpri_gsi,
|
|
&xm_ecpri_dma, &qns_anoc_snoc_gsi,
|
|
&qns_ecpri_gemnoc
|
|
},
|
|
};
|
|
|
|
static struct qcom_icc_bcm bcm_sn7 = {
|
|
.name = "SN7",
|
|
.voter_idx = 0,
|
|
.num_nodes = 2,
|
|
.nodes = { &qns_pcie_gemnoc, &xs_pcie },
|
|
};
|
|
|
|
static struct qcom_icc_bcm *clk_virt_bcms[] = {
|
|
&bcm_qup0,
|
|
};
|
|
|
|
static struct qcom_icc_node *clk_virt_nodes[] = {
|
|
[MASTER_QUP_CORE_0] = &qup0_core_master,
|
|
[MASTER_QUP_CORE_1] = &qup1_core_master,
|
|
[SLAVE_QUP_CORE_0] = &qup0_core_slave,
|
|
[SLAVE_QUP_CORE_1] = &qup1_core_slave,
|
|
};
|
|
|
|
static char *clk_virt_voters[] = {
|
|
"hlos",
|
|
};
|
|
|
|
static struct qcom_icc_desc cinder_clk_virt = {
|
|
.config = &icc_regmap_config,
|
|
.nodes = clk_virt_nodes,
|
|
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
|
|
.bcms = clk_virt_bcms,
|
|
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
|
|
.voters = clk_virt_voters,
|
|
.num_voters = ARRAY_SIZE(clk_virt_voters),
|
|
};
|
|
|
|
static struct qcom_icc_bcm *gem_noc_bcms[] = {
|
|
&bcm_sh0,
|
|
&bcm_sh1,
|
|
};
|
|
|
|
static struct qcom_icc_node *gem_noc_nodes[] = {
|
|
[MASTER_SYS_TCU] = &alm_sys_tcu,
|
|
[MASTER_APPSS_PROC] = &chm_apps,
|
|
[MASTER_GEMNOC_ECPRI_DMA] = &qnm_ecpri_dma,
|
|
[MASTER_FEC_2_GEMNOC] = &qnm_fec_2_gemnoc,
|
|
[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
|
|
[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
|
|
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
|
|
[MASTER_MSS_PROC] = &qxm_mdsp,
|
|
[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
|
|
[SLAVE_LLCC] = &qns_llcc,
|
|
[SLAVE_GEMNOC_MODEM_CNOC] = &qns_modem_slave,
|
|
[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
|
|
};
|
|
|
|
static char *gem_noc_voters[] = {
|
|
"hlos",
|
|
};
|
|
|
|
static struct qcom_icc_desc cinder_gem_noc = {
|
|
.config = &icc_regmap_config,
|
|
.nodes = gem_noc_nodes,
|
|
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
|
|
.bcms = gem_noc_bcms,
|
|
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
|
|
.voters = gem_noc_voters,
|
|
.num_voters = ARRAY_SIZE(gem_noc_voters),
|
|
};
|
|
|
|
static struct qcom_icc_bcm *mc_virt_bcms[] = {
|
|
&bcm_acv,
|
|
&bcm_mc0,
|
|
};
|
|
|
|
static struct qcom_icc_node *mc_virt_nodes[] = {
|
|
[MASTER_LLCC] = &llcc_mc,
|
|
[SLAVE_EBI1] = &ebi,
|
|
};
|
|
|
|
static char *mc_virt_voters[] = {
|
|
"hlos",
|
|
};
|
|
|
|
static struct qcom_icc_desc cinder_mc_virt = {
|
|
.config = &icc_regmap_config,
|
|
.nodes = mc_virt_nodes,
|
|
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
|
|
.bcms = mc_virt_bcms,
|
|
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
|
|
.voters = mc_virt_voters,
|
|
.num_voters = ARRAY_SIZE(mc_virt_voters),
|
|
};
|
|
|
|
static struct qcom_icc_bcm *system_noc_bcms[] = {
|
|
&bcm_ce0,
|
|
&bcm_cn0,
|
|
&bcm_sn0,
|
|
&bcm_sn1,
|
|
&bcm_sn2,
|
|
&bcm_sn7,
|
|
};
|
|
|
|
static struct qcom_icc_node *system_noc_nodes[] = {
|
|
[MASTER_GIC_AHB] = &qhm_gic,
|
|
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
|
|
[MASTER_QPIC] = &qhm_qpic,
|
|
[MASTER_QSPI_0] = &qhm_qspi,
|
|
[MASTER_QUP_0] = &qhm_qup0,
|
|
[MASTER_QUP_1] = &qhm_qup1,
|
|
[MASTER_SNOC_CFG] = &qhm_system_noc_cfg,
|
|
[MASTER_ANOC_SNOC] = &qnm_aggre_noc,
|
|
[MASTER_ANOC_GSI] = &qnm_aggre_noc_gsi,
|
|
[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
|
|
[MASTER_GEMNOC_MODEM_CNOC] = &qnm_gemnoc_modem_slave,
|
|
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
|
|
[MASTER_CRYPTO] = &qxm_crypto,
|
|
[MASTER_ECPRI_GSI] = &qxm_ecpri_gsi,
|
|
[MASTER_PIMEM] = &qxm_pimem,
|
|
[MASTER_SNOC_ECPRI_DMA] = &xm_ecpri_dma,
|
|
[MASTER_GIC] = &xm_gic,
|
|
[MASTER_PCIE] = &xm_pcie,
|
|
[MASTER_QDSS_ETR] = &xm_qdss_etr0,
|
|
[MASTER_QDSS_ETR_1] = &xm_qdss_etr1,
|
|
[MASTER_SDCC_1] = &xm_sdc,
|
|
[MASTER_USB3] = &xm_usb3,
|
|
[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0_south,
|
|
[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1_north,
|
|
[SLAVE_AHB2PHY_EAST] = &qhs_ahb2phy2_east,
|
|
[SLAVE_AOSS] = &qhs_aoss,
|
|
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
|
|
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
|
|
[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
|
|
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto_cfg,
|
|
[SLAVE_ECPRI_CFG] = &qhs_ecpri_cfg,
|
|
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
|
|
[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
|
|
[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
|
|
[SLAVE_PCIE_CFG] = &qhs_pcie_cfg,
|
|
[SLAVE_PDM] = &qhs_pdm,
|
|
[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
|
|
[SLAVE_PRNG] = &qhs_prng,
|
|
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
|
|
[SLAVE_QPIC] = &qhs_qpic,
|
|
[SLAVE_QSPI_0] = &qhs_qspi,
|
|
[SLAVE_QUP_0] = &qhs_qup0,
|
|
[SLAVE_QUP_1] = &qhs_qup1,
|
|
[SLAVE_SDCC_2] = &qhs_sdc2,
|
|
[SLAVE_SMBUS_CFG] = &qhs_smbus_cfg,
|
|
[SLAVE_SNOC_CFG] = &qhs_system_noc_cfg,
|
|
[SLAVE_TCSR] = &qhs_tcsr,
|
|
[SLAVE_TLMM] = &qhs_tlmm,
|
|
[SLAVE_TME_CFG] = &qhs_tme_cfg,
|
|
[SLAVE_TSC_CFG] = &qhs_tsc_cfg,
|
|
[SLAVE_USB3_0] = &qhs_usb3,
|
|
[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
|
|
[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
|
|
[SLAVE_ANOC_SNOC_GSI] = &qns_anoc_snoc_gsi,
|
|
[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
|
|
[SLAVE_ECPRI_GEMNOC] = &qns_ecpri_gemnoc,
|
|
[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
|
|
[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
|
|
[SLAVE_MODEM_OFFLINE] = &qns_modem,
|
|
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc,
|
|
[SLAVE_IMEM] = &qxs_imem,
|
|
[SLAVE_PIMEM] = &qxs_pimem,
|
|
[SLAVE_SERVICE_SNOC] = &srvc_system_noc,
|
|
[SLAVE_ETHERNET_SS] = &xs_ethernet_ss,
|
|
[SLAVE_PCIE_0] = &xs_pcie,
|
|
[SLAVE_QDSS_STM] = &xs_qdss_stm,
|
|
[SLAVE_TCU] = &xs_sys_tcu_cfg,
|
|
};
|
|
|
|
static char *system_noc_voters[] = {
|
|
"hlos",
|
|
};
|
|
|
|
static struct qcom_icc_desc cinder_system_noc = {
|
|
.config = &icc_regmap_config,
|
|
.nodes = system_noc_nodes,
|
|
.num_nodes = ARRAY_SIZE(system_noc_nodes),
|
|
.bcms = system_noc_bcms,
|
|
.num_bcms = ARRAY_SIZE(system_noc_bcms),
|
|
.voters = system_noc_voters,
|
|
.num_voters = ARRAY_SIZE(system_noc_voters),
|
|
};
|
|
|
|
static int qnoc_probe(struct platform_device *pdev)
|
|
{
|
|
int ret;
|
|
|
|
ret = qcom_icc_rpmh_probe(pdev);
|
|
if (ret)
|
|
dev_err(&pdev->dev, "failed to register ICC provider\n");
|
|
else
|
|
dev_info(&pdev->dev, "Registered CINDER ICC\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct of_device_id qnoc_of_match[] = {
|
|
{ .compatible = "qcom,cinder-clk_virt",
|
|
.data = &cinder_clk_virt
|
|
},
|
|
{ .compatible = "qcom,cinder-gem_noc",
|
|
.data = &cinder_gem_noc
|
|
},
|
|
{ .compatible = "qcom,cinder-mc_virt",
|
|
.data = &cinder_mc_virt
|
|
},
|
|
{ .compatible = "qcom,cinder-system_noc",
|
|
.data = &cinder_system_noc
|
|
},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
|
|
|
static struct platform_driver qnoc_driver = {
|
|
.probe = qnoc_probe,
|
|
.remove = qcom_icc_rpmh_remove,
|
|
.driver = {
|
|
.name = "qnoc-cinder",
|
|
.of_match_table = qnoc_of_match,
|
|
.sync_state = qcom_icc_rpmh_sync_state,
|
|
},
|
|
};
|
|
|
|
static int __init qnoc_driver_init(void)
|
|
{
|
|
return platform_driver_register(&qnoc_driver);
|
|
}
|
|
core_initcall(qnoc_driver_init);
|
|
|
|
MODULE_DESCRIPTION("Cinder NoC driver");
|
|
MODULE_LICENSE("GPL v2");
|